1. Field of the Invention
The present invention generally relates to the design of integrated circuits, and more particularly to a method of inserting spare cells in an integrated circuit design to accommodate engineering changes.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells.
An IC chip is fabricated by first conceiving a logical (behavioral) description for the circuit, and converting that logical description into a physical description, or geometric layout. This process is carried out in steps, such as first generating a register-transfer level (RTL) description of the circuit based on the logical description, and then using logic synthesis to derive a gate level description or “netlist.” A netlist is a record of all of the nets (interconnections) between cell pins, including information about the various components such as transistors, resistors and capacitors. The circuit layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements, and may go through several iterations of analysis and refinement.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located in a layer of an integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices such as microprocessors and application-specific integrated circuits (ASICs), physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different hardware-description programming languages (HDL) have been created for electronic design automation, including Verilog, C, VHDL and TDML. A typical electronic design automation system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Once a design is mostly finished, slight modifications may still be required to meet last-minute changes to specifications or for other reasons, usually relayed as an engineering change order (ECO). Because the circuit design is substantially complete (i.e., it conforms to various design requirements such as timing and slew), it is important to minimize the impact of any changes which might otherwise lead to violations and thus require additional iterations of the design steps, meaning significant computational expense. In order to alleviate this predicament, designers place filler (ECO) cells in the circuit design which have no function other than providing spare locations as needed for later changes. These spare locations can be provided in additional to surplus latches or other components that are inserted in a design. A certain percentage of the total number of cells is typically designated for filler cells, and those cells are randomly placed throughout the layout.